library ieee;
use ieee.std_logic_1164.all;
use work.mis_componentes.all;

entity complemento2 is
port(a,b,c,d:in std_logic;
	f:out std_logic_vector(3 downto 0);
	Cout:out std_logic);
	
end complemento2;


architecture bhv of complemento2 is
signal dim:std_logic_vector(3 downto 0);
begin
dim<=not(a)&not(b)&not(c)&not(d);
U1: sum4bits PORT MAP(dim,"0001",f,Cout);
end bhv;